US 10,763,277 B2Granted

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorsGo Oike, Tsuyoshi Sugisaki

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Abstract

According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Claims17

Dependent claims

A semiconductor memory device comprising:

a plurality of first interconnect layers stacked in a first direction;
first and second memory pillars extending in the plurality of first interconnect layers;
and
a plurality of first plugs respectively contacting the plurality of first interconnect layers,
wherein the plurality of first interconnect layers include:
a first region where the first memory pillar extends in the plurality of first interconnect layers;
a second region where the second memory pillar extends in the plurality of first interconnect layers;
and
a third region where the plurality of first plugs are respectively contacted to one of the plurality of first interconnect layers, and
the first region, the third region, and the second region are arranged in order along a second direction crossing the first direction.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/118,598Filed 31 Aug 2018
Priority: JP 2018-04694014 Mar 2018
Published: US 2019/0287995 A119 Sep 2019
Granted: 1 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits

Family

US 2019/0287995 A1Pre-grant publication · published 19 Sep 2019
US 10,763,277 B2This patent

From the US filing history. Foreign family members aren’t listed.

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