Stacked package structure and stacked packaging method for chip
AssigneeSilergy Semiconductor Technology (Hangzhou) LTD
InventorXiaochun Tan
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AssigneeSilergy Semiconductor Technology (Hangzhou) LTD
InventorXiaochun Tan
Estimating the term…
A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.
A stacked package structure, comprising:
A method of making a stacked package structure, the method comprising:
Dependencies are inferred from the claim text.