Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a first interlayer dielectric (ILD) layer disposed over a substrate;
• a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate,
• wherein the first metal wiring pattern includes a first lower portion and a first upper portion;
• a second ILD layer disposed over the first ILD layer and the first metal wiring pattern;
• and
• a second metal wiring pattern formed in the second ILD layer and connected to the first metal wiring pattern,
• wherein the second metal wiring pattern includes a second lower portion and a second upper portion,
• in a cross section along a second direction, which crosses the first direction and is in parallel with the substrate, a top of the second metal wiring pattern is fully covered by a first two-dimensional material layer,
• the first two-dimensional material layer is a single layer of two-dimensional material, and
• the first two-dimensional material layer is in direct contact with a surface of the second metal wiring pattern,
• wherein in the cross section, sides and bottom of the upper portion of the second metal wiring pattern are covered by a second two-dimensional material layer,
• in the cross section, a part of a top of the first metal wiring pattern is covered by a third two-dimensional material layer, and the second metal wiring pattern passes through the third two-dimensional material layer and is in direct contact with a surface of the first metal wiring pattern,
• in the cross section, sides and bottom of the upper portion of the first metal wiring pattern are covered by a fourth two-dimensional material layer, and
• wherein the first two-dimensional material layer and the second two-dimensional material layer are different materials.

A method of manufacturing a semiconductor device, comprising:

• forming a first interlayer dielectric layer over a substrate;
• forming a first recess in the first interlayer dielectric layer;
• forming a first conductive material layer in a lower portion of the first recess;
• forming a single layer of a first two-dimensional material layer over the first conductive material layer and sidewalls of the first recess above the first conductive material layer;
• forming a first metal layer in the first recess over the first two-dimensional material layer;
• forming a single layer of a second two-dimensional material layer over the first metal layer;
• forming a second interlayer dielectric layer over the second two-dimensional material layer and the first interlayer dielectric layer;
• forming a second recess in the second interlayer dielectric layer exposing the second two-dimensional material layer;
• forming a second conductive material layer in a lower portion of the second recess;
• forming a single layer of a third two-dimensional material layer over the second conductive material layer and sidewalls of the second recess above the second conductive material layer;
• forming a second metal layer in the second recess over the third two-dimensional material layer;
• and
• forming a single layer of a fourth two-dimensional material layer over the second metal layer.