I/O device for gate-all-around transistors

A method of forming an integrated circuit, the method comprising the steps of:

• forming alternating layers of nanosheets of a channel material and a sacrificial material on a wafer;
• patterning the nanosheets into at least a first device stack and a second device stack, wherein the first device stack is a logic device stack, and wherein the second device stack is an I/O device stack;
• selectively removing the nanosheets of the sacrificial material from the first device stack and from the second device stack, releasing the nanosheets of the channel material from the first device stack and from the second device stack;
• forming an IL oxide on the nanosheets of the channel material in the first device stack and in the second device stack;
• depositing a conformal gate dielectric on the nanosheets of the channel material in the first device stack and in the second device stack over the IL oxide;
• selectively forming an oxygen containing layer on the second device stack that pinches off a channel-to-channel space between the nanosheets of the channel material in the second device stack;
• depositing a sacrificial layer onto the nanosheets of the channel material in the first device stack and onto the oxygen containing layer in the second device stack, wherein the sacrificial layer comprises a metal nitride;
• depositing a barrier layer onto and encapsulating the first device stack and the second device stack;
• annealing the first device stack and the second device stack under conditions sufficient to drive oxygen atoms from the oxygen containing layer into the IL oxide in the second device stack;
• removing i) the sacrificial layer and barrier layer from the first device stack, and ii) the oxygen containing layer, sacrificial layer and barrier layer from the second device stack;
• and
• depositing a conformal gate conductor over the gate dielectric in the first device stack and in the second device stack.

An integrated circuit, comprising:

• device stacks having nanosheets of a channel material disposed on a wafer, wherein the device stacks comprise at least a first device stack and a second device stack, wherein the first device stack is a logic device stack, and wherein the second device stack is an I/O device stack;
• an IL oxide formed on the nanosheets of the channel material in the first device stack and in the second device stack, wherein the IL oxide formed on the nanosheets of the channel material in the first device stack has a thickness T1 and the IL oxide formed on the nanosheets of the channel material in the second device stack has a thickness T2 wherein T2>T1;
• a conformal gate dielectric disposed on the nanosheets of the channel material in the first device stack and in the second device stack over the IL oxide;
• and
• a conformal gate conductor disposed over the gate dielectric in the first device stack and in the second device stack, wherein the conformal gate conductor surrounds a portion of each of the nanosheets of the channel material in the first device stack and in the second device stack in a gate-all-around configuration.