Memory with partial array refresh

Abstract

Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

Dependencies are inferred from the claim text.