Adaptive accelerated yield analysis

A system for optimizing statistical methods of computing output yields, the system comprising:

• a processor communicatively coupled to a memory, the processor configured to:
• determine a target criteria of a circuit design for statistical analysis;
• based at least in part on the target criteria, determine a statistical analysis algorithm for the statistical analysis;
• determine a block size for a plurality of statistical samples of the circuit design for a parallelization of the statistical analysis algorithm;
• generate the plurality of statistical samples of the circuit design;
• simulate the plurality of statistical samples of the circuit design to determine one or more output yields;
• calculate a confidence interval for each of the one or more output yields, wherein the confidence interval comprises a lower bound;
• compare the lower bound to a threshold standard deviation of a probability density function;
• adjust the block size for the plurality of statistical samples of the circuit design based on determining that the lower bound is less than the threshold standard deviation of the probability density function;
• generate a block of new statistical samples of the circuit design, wherein the block comprises the adjust block size;
• perform a simulation utilizing the block of new statistical samples of the circuit design;
• and
• determine a result of the simulation;
• and
• manufacturing a circuit based on based on the result of the simulation.

A computer program product for optimizing simulation output yields comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

• determining a target criteria of a circuit design for statistical analysis;
• based at least in part on the target criteria, determining a statistical analysis algorithm for the statistical analysis;
• determining a block size for a plurality of statistical samples of the circuit design for a parallelization of the statistical analysis algorithm;
• generating the plurality of statistical samples of the circuit design;
• simulating the plurality of statistical samples of the circuit design to determine one or more output yields;
• calculating a confidence interval for each of the one or more output yields, wherein the confidence interval comprises a lower bound;
• comparing the lower bound to a threshold standard deviation of a probability density function;
• adjusting the block size for the plurality of statistical samples of the circuit design based on determining that the lower bound is less than the threshold standard deviation of the probability density function;
• generating a block of new statistical samples of the circuit design, wherein the block comprises the adjust block size;
• performing a simulation utilizing the block of new statistical samples of the circuit design;
• determining a result of the simulation;
• and
• manufacturing a circuit based on based on the result of the simulation.