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US 10,762,012 B2Granted
Memory system for sharing a plurality of memories through a shared channel
AssigneeSK hynix Inc.
InventorDong Uk Lee
Life of this patent
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Abstract
A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.
Claims19
A memory system comprising:
- a first chip configured to perform a first operation;
- a second chip configured to perform a second operation;
- a stacked memory device configured to include a stacked structure of a plurality of memories, the stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus;
- a first interface circuit coupling the first chip to the shared bus;
- and
- a second interface circuit coupling the second chip to the shared bus,
- wherein the shared bus includes:
- a first shared bus through which the first interface circuit and the second interface circuit are electrically coupled to each other;
- and
- a second shared bus through which the first shared bus is coupled to the plurality of memories.
7 more elements
Dependencies are inferred from the claim text.