Quadrature relaxation oscillator using frequency error compensation loop
AssigneePostech Academy-Industry Foundation
InventorsJae Yoon Sim, Ja Hyun Koo
Life of this patent
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Abstract
The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.
Claims8
A quadrature relaxation oscillator using a frequency error compensation loop, comprising:
- a charge control unit configured to provide a charge path or a discharge path for generating an I clock signal and a Q clock signal at a corresponding phase among first to fourth phases;
- a charge unit configured to charge a power supply voltage supplied through the charge path or discharge a previously-charged voltage through the discharge path, and output corresponding first and second charge/discharge voltages;
- a reference voltage generation unit configured to output first and second upper reference voltages and first and second lower reference voltages by applying a frequency compensation method, wherein the reference voltage generation unit compares the first and second charge/discharge voltages with upper and lower reference voltages, respectively, at phases at which levels of the first and second charge/discharge voltages are stopped, and outputs the first and second upper reference voltages and the first and second lower reference voltages which are synchronized with the first and second charge/discharge voltages;
- a comparison unit configured to compare the first charge/discharge voltage with the first upper and lower reference voltages and compare the second charge/discharge voltage with the second upper and lower reference voltages, and output corresponding respective logic signals;
- and
- an S-R latch unit configured to latch the respective logic signals and output the I clock signal and the Q clock signal corresponding thereto.
Dependencies are inferred from the claim text.