Semiconductor device including dielectric layer

A semiconductor device, comprising:

• a stack structure on a substrate, the stack structure including interlayer insulating layers and word lines alternately stacked on each other;
• a hole penetrating through the stack structure;
• a vertical structure disposed in the hole, the vertical structure including a semiconductor layer in the hole, a first dielectric layer between the semiconductor layer and the stack structure, and a pad contacting an upper region of the semiconductor layer;
• and
• a lower pattern closer to the substrate than to the word lines,
• wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the lower pattern and having a thickness greater than a thickness of the first portion, and
• wherein the hole includes a first hole region and a second hole region below the first hole region, the first hole region having a shape closer to a circular shape than a shape of the second hole region thereto, and the second hole region including a concave portion and a convex portion on a same plane.

A semiconductor device, comprising:

• a stack structure on a substrate, the stack structure including interlayer insulating layers and word lines alternately stacked on each other;
• a hole penetrating through the stack structure;
• a vertical structure disposed in the hole, the vertical structure including a semiconductor layer in the hole, a first dielectric layer between the semiconductor layer and the stack structure, and a pad contacting an upper region of the semiconductor layer;
• and
• a lower pattern closer to the substrate than to the word lines,
• wherein the first dielectric layer includes:
• a first portion extending along a depth direction of the hole and facing the stack structure, and
• a second portion extending from a bottom of the first portion toward a central axis of the hole, the second portion facing the lower pattern and having a thickness greater than a thickness of the first portion, and
• wherein the lower pattern includes a recessed portion recessed from an upper portion of the lower pattern, the recessed portion being in contact with the semiconductor layer.