Delay circuit with dual delay resolution regime
AssigneeKiskeya Microsystems LLC
InventorMarc Péralte Dandin
Life of this patent
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Abstract
A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.
Claims20
A delay circuit, comprising:
- a first regulator configured to cause only a first edge of an input signal to the delay circuit to be actively delayed by the delay circuit, wherein a second edge of the input signal is not actively delayed when the first regulator is enabled;
- a second regulator configured to cause only the second edge of the input signal to be actively delayed by the delay circuit, wherein the first edge of the input signal is not actively delayed when the second regulator is enabled;
- and
- a selection terminal, which when energized with a digital voltage, enables one of the first regulator and the second regulator and disables the other one of the first regulator and the second regulator.
A hold-off circuit, comprising:
- a delay line including a set of delay circuits disposed in series, wherein a delay circuit in the set includes:
- a first regulator, programmable to be enabled by a first digital voltage, the first regulator configured to cause only a first edge of an input signal to the delay circuit to be actively delayed by the delay circuit, wherein a second edge of the input signal is not actively delayed when the first regulator is enabled;
- and
- a second regulator, programmable to be enabled by a second digital voltage being a complement of the first digital voltage, the second regulator configured to cause only the second edge of the input signal to be actively delayed by the delay circuit, wherein the first edge of the input signal is not actively delayed when the second regulator is enabled;
- a selection terminal, which, when energized with the first digital voltage, enables the first regulator and disables the second regulator, and which, when energized with the second digital voltage, enables the second regulator and disables the first regulator.
A delay circuit, comprising:
- a first current regulator;
- a second current regulator;
- wherein the first current regulator is configured to cause the delay circuit to be in a first delay resolution regime when enabled and when the second current regulator is disabled, and
- wherein the second current regulator is configured to cause the delay circuit to be in a second delay resolution regime distinct from the first delay resolution regime, when the second current regulator is enabled and the first current regulator is disabled.
Dependencies are inferred from the claim text.