Etching process control in forming MIM capacitor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Abstract
A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
Claims20
A method comprising:
- forming a capacitor comprising:
- depositing a bottom electrode layer;
- depositing a capacitor insulator layer over the bottom electrode layer;
- depositing a top electrode layer over the capacitor insulator layer;
- depositing a first dielectric layer over the top electrode layer;
- etching the first dielectric layer using a first etching gas until the top electrode layer is exposed, wherein the first dielectric layer is etched using a first etching mask;
- etching the top electrode layer using the first etching mask to form a top electrode;
- despositing a second dielectric layer over the top electrode;
- and
- etching the second dielectric layer, the capacitor insulator layer and the bottom electrode layer using a same second etching mask to form a capacitor insulator and a bottom electrode, respectively;
- and
- forming a top contact penetrating through the first dielectric layer to contact the top electrode.
A method comprising:
- depositing a bottom electrode layer on a wafer;
- depositing a capacitor insulator layer over the bottom electrode layer;
- depositing a top electrode layer over the capacitor insulator layer;
- depositing a first dielectric layer over the top electrode layer;
- etching the first dielectric layer using a first etching gas, wherein the first etching gas comprises CF4, and is substantially free from additional carbon-and-fluorine-containing gases;
- etching the top electrode layer using a second etching gas to form a top electrode;
- forming a second dielectric layer on a top surface of the first dielectric layer and sidewalls of the top electrode;
- and
- etching the second dielectric layer, the capacitor insulator layer, and the bottom electrode layer using a same etching mask.
A method comprising:
- depositing a bottom electrode layer on a wafer;
- depositing a capacitor insulator layer over the bottom electrode layer;
- depositing a top electrode layer over the capacitor insulator layer;
- depositing a first dielectric layer over the top electrode layer;
- etching the first dielectric layer until the top electrode layer is exposed;
- etching the top electrode layer to form a top electrode, wherein the top electrode has a footing profile, with lower portions of the top electrode being increasingly wider than respective upper portions of the top electrode;
- forming a second dielectric layer covering the top electrode and a remaining portion of the first dielectric layer;
- and
- patterning the second dielectric layer, the capacitor insulator layer, and the bottom electrode layer to form a capacitor, wherein remaining portions of the second dielectric layer, the capacitor insulator layer, and the bottom electrode layer extend beyond edges of the remaining portion of the first dielectric layer.
Dependencies are inferred from the claim text.