Programmable buried antifuse
AssigneeInternational Business Machines Corporation
InventorsPraneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
Life of this patent
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Abstract
An antifuse is provided that is embedded in a semiconductor substrate. The antifuse has a large contact area, and a reduced breakdown voltage. After blowing the antifuse, the antifuse has a low resistance. The antifuse may have a single breakdown point or multiple breakdown points. The antifuse includes a metal or metal alloy structure that is separated from a doped semiconductor material portion of the semiconductor substrate by an antifuse dielectric material liner. The metal or metal alloy structure and the antifuse dielectric material liner have topmost surfaces that are coplanar with each other as well as being coplanar with a topmost surface of the semiconductor substrate.
Claims12
A semiconductor structure comprising:
- an antifuse having faceted sidewalls that converge at a point and embedded in a semiconductor substrate, the antifuse comprising a metal or metal alloy structure present in a doped semiconductor material portion of the semiconductor substrate, wherein an antifuse dielectric material liner is present between the doped semiconductor material portion and the metal or metal alloy structure, and wherein each of the metal or metal alloy structure and the antifuse dielectric material liner has faceted sidewall surfaces, a shape selected from the group consisting of a sigma shape, a diamond shape and a triangular shape, and a topmost surface that is coplanar with each other and coplanar with a topmost surface of the semiconductor substrate.
A method of forming a semiconductor structure, the method comprising:
- providing an opening having faceted sidewalls that converge at a point and within a doped semiconductor material portion of a semiconductor substrate;
- and
- forming an antifuse dielectric material liner and a metal or metal alloy structure in the opening, wherein each of the antifuse dielectric material liner and the metal or metal alloy structure has faceted sidewall surfaces and a shape selected from the group consisting of a sigma shape, a diamond shape and a triangular shape.
A semiconductor structure comprising:
- an antifuse having a bottom wall that converges at a point and embedded in a semiconductor substrate, the antifuse comprising a metal or metal alloy structure present in a doped semiconductor material portion of the semiconductor substrate, wherein an antifuse dielectric material liner is present between the doped semiconductor material portion and the metal or metal alloy structure, and wherein each of the metal or metal alloy structure and the antifuse dielectric material liner has a bottom wall surface, a shape selected from the group consisting of a diamond shape and a triangular shape, and a topmost surface that is coplanar with each other and coplanar with a topmost surface of the semiconductor substrate.
Dependencies are inferred from the claim text.