High speed frequency divider
AssigneeXilinx, Inc.
InventorsYipeng Wang, Kee Hian Tan, Stanley Y. Chen, Yohan Frans
Life of this patent
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Abstract
A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.
Claims19
A frequency divider comprising:
- a frequency sub-divider including an input to receive an input clock and including an output to provide a frequency divided clock;
- a delay circuit including a plurality of single-edge triggered flip-flops connected in series, and configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock;
- and
- a logic gate including a first input to receive the frequency divided clock, including a second input to receive the delayed clock, and configured to perform a logical AND operation or a logical NAND operation on the frequency divided clock and the delayed clock to generate an output clock having a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, wherein N is an integer greater than one.
A frequency divider comprising:
- an input to receive an input clock;
- an output circuit to generate an output clock having a frequency that is equal to 1/5.5 times a frequency of the input clock;
- a frequency sub-divider having an input to receive the input clock and configured to generate a frequency divided clock having a frequency equal to 1/11 times the frequency of the input clock;
- and
- a delay circuit including six single-edge triggered flip-flops coupled in series between the frequency sub-divider and the output circuit, wherein a first five of the six single-edge triggered flip-flops are clocked on first edges of the input clock, and a sixth single-edge triggered flip-flop is clocked on second edges of the input clock.
A method for generating an output clock having a frequency that is equal to 1/(N+0.5) times a frequency of an input clock, the method comprising:
- frequency-dividing the input clock to generate a frequency divided clock using a number of cascaded divide-by-four frequency dividers;
- delaying the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock using a plurality of single-edge triggered flip-flops;
- and
- logically combining, using a logical AND operation or a logical NAND operation, the frequency divided clock and the delayed clock to generate the output clock, wherein N is an integer greater than one.
Dependencies are inferred from the claim text.