US 10,504,944 B2Granted

Thin film transistor and display substrate, fabrication method thereof, and display device

AssigneeBoe Technology Group Co., Ltd.

InventorsShi Shu, Chuanxiang Xu, Teng Luo, Feng Gu, Bin Zhang

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Abstract

A method for fabricating a thin film transistor includes providing a substrate (100); forming a semiconductor layer (105) over the substrate (100); forming a source-drain metal layer (106) over the semiconductor layer (105); applying one patterning process to the semiconductor layer (105) and the source-drain metal layer (106) to form an active layer (1), a source electrode (2), and a drain electrode (3); forming a gate insulating layer (101) and an interlayer insulating layer (102) that cover the active layer (1), the source electrode (2), and the drain electrode (3); applying a patterning process to the interlayer insulating layer (102) to form a first window (10) in the interlayer insulating layer (102) to expose a portion of the gate insulating layer (101); and forming a gate electrode (4) in the first window (10). An orthogonal projection of the gate electrode (4) on the substrate (100) is in an orthogonal projection of the active layer (1) on the substrate (100).

Claims8

Dependent claims

A method for fabricating a display substrate, comprising a method for fabricating a thin film transistor, the method for fabricating the thin film transistor comprising:

providing a substrate;
forming a semiconductor layer over the substrate;
forming a source-drain metal layer over the semiconductor layer;
applying one patterning process to the semiconductor layer and the source-drain metal layer to form an active layer, a source electrode, and a drain electrode;
forming a gate insulating layer and an interlayer insulating layer that cover the active layer, the source electrode, and the drain electrode;
applying a patterning process to the interlayer insulating layer to form a first window in the interlayer insulating layer to expose a portion of the gate insulating layer;
and
forming a gate electrode in the first window, an orthogonal projection of the gate electrode on the substrate being in an orthogonal projection of the active layer on the substrate;
and
wherein the method for fabricating the display substrate further comprises:
forming a passivation layer over the thin film transistor;
forming a first via hole and a second via hole penetrating through the passivation layer, the interlayer insulating layer, and the gate insulating layer;
forming a transparent conductive layer over the passivation layer and in the first via hole and the second via hole;
and
patterning the transparent conductive layer to form a pixel electrode and a first electrode, the pixel electrode being electrically coupled to the drain electrode through the first via hole and the first electrode being electrically coupled to the source electrode through the second via hole.

12 more elements

A display substrate comprising a thin film transistor, the thin film transistor comprising:

a substrate;
an active layer over the substrate;
a source electrode and a drain electrode over the substrate,
wherein:
the source electrode and the drain electrode are disposed over a surface of the active layer facing away from the substrate, and
orthogonal projections of the source electrode and the drain electrode on the substrate are in an orthogonal projection of the active layer on the substrate;
a gate insulating layer covering the active layer, the source electrode, and the drain electrode;
an interlayer insulating layer over the gate insulating layer, the interlayer insulating layer having a first window exposing a portion of the gate insulating layer;
and
a gate electrode in the first window, an orthogonal projection of the gate electrode on the substrate being located in the orthogonal projection of the active layer on the substrate;
wherein the display substrate further comprises:
a passivation layer over the thin film transistor;
and
a pixel electrode and a first electrode in a same layer and over the passivation layer, wherein:
the pixel electrode is electrically coupled to the drain electrode through a first via hole penetrating through the passivation layer, the interlayer insulating layer, and the gate insulating layer, and
the first electrode is electrically coupled to the source electrode through a second via hole penetrating through the passivation layer, the interlayer insulating layer, and the gate insulating layer.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/768,634Filed 30 Oct 2017
Priority: CN 2017 1 019733229 Mar 2017
Published: US 2019/0067340 A128 Feb 2019
Granted: 10 Dec 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

H01L 27/1288
G02F 1/1362
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit: active…
G02F 1/1368
Active matrix addressed cells: in which the switching element is a three-electrode device
G02F 1/136227
Active matrix addressed cells: through-hole connection of the pixel electrode to the active element through an insulation layer

Family

US 2019/0067340 A1Pre-grant publication · published 28 Feb 2019
US 10,546,885 B2Related patent
US 10,504,944 B2This patent

From the US filing history. Foreign family members aren’t listed.

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