Memory cell having closed curve structure
AssigneeHewlett-Packard Development Company, L.P.
InventorsReynaldo V. Villavelez, Paul I. Mikulan
Life of this patent
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Abstract
A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.
Claims18
A memory cell for a printhead, the memory cell comprising:
- a substrate including a drain and a source, the drain having a first rounded closed curve structure;
- a channel within the substrate and located between the drain and the source, the channel surrounding the drain;
- a floating gate formed in a polysilicon layer and having a second rounded closed curve structure located above the channel;
- a control gate formed in a first metal layer provided over the substrate after the polysilicon layer is provided over the substrate, the control gate capacitively coupled to the floating gate and located above the floating gate;
- and
- a capacitor plate formed in a second metal layer different from the first metal layer, the capacitor plate electrically connected to the floating gate, the control gate capacitively coupled to the capacitor plate.
An EPROM array for a printhead, comprising:
- a matrix of EPROM memory cells, wherein each EPROM memory cell includes:
- a substrate including a drain and a source, the drain having a rounded closed curve structure;
- a channel within the substrate and located between the drain and the source, the channel surrounding the drain;
- a floating gate formed in a polysilicon layer and having a second rounded closed curve structure located above the channel;
- a control gate formed in a first metal layer provided over the substrate after the polysilicon layer is provided over the substrate, the control gate capacitively coupled to the floating gate and located above the floating gate;
- and
- a capacitor plate formed in a second metal layer different from the first metal layer, the capacitor plate electrically connected to the floating gate, the control gate capacitively coupled to the capacitor plate.
Dependencies are inferred from the claim text.