High reliability OTP memory by using of voltage isolation in series

A high reliable OTP memory by using of Voltage Isolation in Series, comprising:

• a first MOS transistor, a second MOS transistor and a anti-fuse element, wherein
• a gate of the first MOS transistor is connected to a second line WS, a first end of the first MOS transistor is connected to a gate of the second MOS transistor, and to a voltage limit device, a second end of the first MOS transistor is connected to a third line BL;
• a first end of the second MOS transistor is connected to a fourth line BR, and a second end of the second MOS transistor is connected to the third line BL, the gate of the second MOS transistor is connected to the voltage limit device and to the second end of the first MOS transistor;
• the high reliable OTP memory by using of Voltage Isolation in Series further comprises the voltage-limit device having one control end and two connection ends, the control end of the voltage-limit device is connected to a control line WB, a first connection end of the voltage-limit device is connected to the anti-fuse element and a first line WP across through the anti-fuse element, a second connection end of the voltage-limit device is connected to the gate of the second MOS transistor and to the first end of the first MOS transistor.