Integrated circuit comprising balanced cells at the active
AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
InventorsFrancois Andrieu, Remy Berthelon
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AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
InventorsFrancois Andrieu, Remy Berthelon
Estimating the term…
An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.
An integrated circuit, comprising:
Dependencies are inferred from the claim text.