Back to results
US 10,504,896 B2Granted
HVMOS reliability evaluation using bulk resistances as indices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Feng Huang, Chia-Chung Chen, Tse-Hua Lu
Life of this patent
Estimating the term…
Abstract
A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.
Claims20
A structure comprising:
- a semiconductor substrate;
- a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed at a surface of the semiconductor substrate, wherein the plurality of HVPMOS devices form an array comprising a plurality of rows and a plurality of columns;
- and
- an n-type guard ring comprising a plurality of portions, each encircling one of the plurality of HVPMOS devices, with neighboring ones of the plurality of HVPMOS devices separated from each other by the n-type guard ring.
1 more element
A structure comprising:
- a semiconductor substrate;
- a heavily doped semiconductor region extending into the semiconductor substrate wherein the heavily doped semiconductor region forms a guard ring;
- a plurality of isolation regions extending into the semiconductor substrate and forming an array, wherein each of the plurality of isolation regions is separated from other ones of the plurality of isolation regions by the heavily doped semiconductor region;
- a plurality of active regions, each encircled by one of the plurality of isolation regions, wherein the plurality of active regions have active-region-to-guard-ring spacings smaller than about 2 pm;
- and
- a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed based on the plurality of active regions.
3 more elements
A structure comprising:
- a semiconductor substrate;
- a heavily doped semiconductor region extending into the semiconductor substrate, wherein the heavily doped semiconductor region is of n-type;
- a plurality of Shallow Trench Isolation (STI) regions extending into the semiconductor substrate and forming an array, wherein each of the plurality of STI regions is separated from other ones of the plurality of STI regions by the heavily doped semiconductor region;
- a plurality of active regions, each encircled by one of the plurality of STI regions, wherein each of the plurality of STI regions has a rectangular top-view shape, and has a length and a width smaller than the length, with the width being smaller than about 30 μm;
- and
- a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices, each being formed based on one of the plurality of active regions.
3 more elements
Dependencies are inferred from the claim text.