Semiconductor device and a manufacturing method therefor

A semiconductor device, comprising:

• a semiconductor body comprising a first side defining a vertical direction, and a second side opposite the first side;
• an active area;
• an inactive area which is, in a projection onto to the first side, adjacent to the active area;
• a dielectric structure arranged on the first side;
• a source terminal formed on the dielectric structure;
• a gate terminal formed on the dielectric structure;
• a transistor cell formed in the active area and comprising a source region in Ohmic connection with the source terminal overlapping with the source region in the projection, and disposed in the semiconductor body, and a gate electrode insulated from the semiconductor body, in Ohmic connection with the gate terminal, and overlapping with the source terminal in the projection;
• and
• a capacitor formed in the inactive area, embedded in the dielectric structure, and comprising a first conductor in Ohmic connection with the source terminal and a second conductor in Ohmic connection with the gate terminal, wherein a distance in the vertical direction between the first conductor and the second conductor is less than about 200 nm.

A method for manufacturing a semiconductor device comprising a transistor, the method comprising:

• providing a semiconductor body comprising a first side, a second side opposite the first side, an active area, an inactive area being, in a projection onto a horizontal plane substantially parallel to the first side and/or the second side, adjacent to the active area, and a source region adjacent to the first side, and extending to a first pn-junction arranged in the active area;
• forming a dielectric structure comprising two embedded conductive layers on the first side so that a first layer of the two conductive layers is arranged in the inactive area and that a second layer of the two conductive layers comprises a first portion forming a gate electrode overlapping in the projection onto the horizontal plane with the first pn-junction, and a second portion spaced apart from and overlapping in the projection onto the horizontal plane with the first conductive layer so that a vertical distance between the first conductive layer and the second portion is less than about 200 nm;
• and
• forming on the dielectric structure a source terminal in Ohmic connection with the source region and the first layer.