Integrating a junction field effect transistor into a vertical field effect transistor

A method of fabricating semiconductor devices, the method comprising:

• performing fabrication operations to form a first transistor device on a substrate, wherein the fabrication operations to form the first transistor device comprise:
• forming one or more fins on the substrate;
• forming a bottom source or drain (S/D) region on the substrate;
• forming a bottom spacer on the bottom S/D region;
• forming a dielectric layer over the one or more fins;
• forming a metal gate for the one or more fins over the dielectric layer;
• forming a cap layer over the bottom spacer and metal gate;
• and
• forming a top S/D region over the one or more fins;
• and
• performing fabrication operations to form a second transistor device on the substrate, wherein the fabrication operations to form the second transistor device comprise:
• forming a bottom region of the second transistor device on the substrate;
• forming the channel region on the bottom region, wherein the one or more fins of the first transistor device are formed with the channel region of the second transistor device;
• forming the bottom spacer;
• forming sidewalls of the channel region of the second transistor device;
• forming a metal gate for the second transistor device, wherein the metal gate for the second transistor device is formed with the metal gate for the one or more fins;
• forming the cap layer over bottom spacer and the metal gate of the second transistor device;
• forming the top region over the sidewalls and the channel region;
• and
• forming one or more contacts over the top region.