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US 10,504,854 B2Granted
Through-stiffener inerconnects for package-on-package apparatus and methods of assembling same
AssigneeIntel Corporation
InventorsBok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Jackson Chung Peng Kong
Life of this patent
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Abstract
A stiffener includes a through-stiffener interconnect that couples a semiconductor package substrate to a package-on-package device. The through-stiffener interconnect is insulated by a through-stiffener dielectric within a through-stiffener contact corridor. A semiconductive die is coupled to the semiconductor package substrate and to the package-on-package device.
Claims4
A semiconductor package, comprising:
- a semiconductor package substrate including a die side and a land side;
- a through-stiffener interconnect (TSI) stiffener disposed on the die side, wherein the TSI stiffener includes a die side and a package-on-package (POP) side, and wherein the TSI stiffener includes a TSI that communicates from the die side to the POP side, wherein the TSI is electrically insulated with a TSI dielectric;
- an electrical connection between the package substrate and the TSI;
- a subsequent stiffener disposed on the die side, wherein the TSI stiffener surrounds the subsequent stiffener;
- and
- a passive device bridging between the TSI stiffener and the subsequent stiffener, wherein the TSI stiffener is coupled to a source voltage structure within the semiconductor package substrate.
3 more elements
A computing system, comprising:
- a semiconductor package substrate including a die side and a land side;
- a semiconductive die disposed on the die side;
- a stiffener disposed on the die side, wherein the stiffener includes a die side and a package-on-package (POP) side, and wherein the stiffener includes a first through-stiffener interconnect (TSI) that communicates from the die side to the POP side;
- an electrical connection between the package substrate and the first TSI, wherein the first TSI is located on the stiffener on a first rail portion;
- a POP device seated on the stiffener, wherein the POP device is coupled to the first TSI;
- a subsequent TSI located in the stiffener on a subsequent rail portion that is opposite the first rail portion, wherein the subsequent TSI electrically contacts the semiconductor package substrate and the POP device;
- a third rail portion between the first and subsequent rail portions, and a fourth rail portion opposite the third rail portion;
- and
- a board at which the land side is mounted by at least one electrical bump, and wherein the board includes a dielectric outer shell.
6 more elements
A semiconductor package, comprising:
- a semiconductor package substrate including a die side and a land side;
- a stiffener disposed on the die side, wherein the stiffener includes a die side and a package-on-package (POP) side, and wherein the stiffener includes a first through-stiffener interconnect (TSI) that communicates from the die side to the POP side, wherein the first TSI is electrically insulated with a TSI dielectric, and wherein the first TSI is on a first rail portion of the stiffener;
- an electrical connection between the package substrate and the first TSI, wherein the electrical connection is coupled to at least one of a power or input/output (I/O) connection, further including wherein the stiffener also is coupled to the semiconductor package substrate at a source voltage structure;
- a subsequent TSI located in the stiffener on a subsequent rail portion that is opposite the first rail portion;
- and
- a semiconductive die disposed on the semiconductor package substrate die side, wherein the semiconductive die is coupled to the first TSI
- a board at which the land side is mounted by at least one electrical bump, and wherein the board includes a dielectric outer shell;
- and
- wherein the semiconductive die is a first semiconductive die, and further including a subsequent semiconductive die disposed above the semiconductor package substrate die side, and wherein the first semiconductive die and the subsequent semiconductive die are part of a chipset.
6 more elements
Dependencies are inferred from the claim text.