Three-dimensional integrated circuit structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJie Chen, Hsien-Wei Chen, Ying-Ju Chen
Life of this patent
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Abstract
Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.
Claims19
A three-dimensional integrated circuit structure, comprising:
- a first die comprising a first integrated circuit region, a first seal ring region around the first integrated circuit region, and a first alignment mark within the first integrated circuit region;
- and
- a second die bonded to the first die, comprising a second integrated circuit region, a second seal ring region around the second integrated circuit region, and a second alignment mark within the second seal ring region and corresponding to the first alignment mark, wherein the first die further comprises a plurality of first seal ring patterns within the first seal ring region and outside of the second seal ring region from a top view.
A three-dimensional integrated circuit structure, comprising:
- a first die comprising a first integrated circuit region, a first seal ring region around the first integrated circuit region, and a first alignment mark within the first integrated circuit region;
- and
- a second die bonded to the first die, comprising a second integrated circuit region, a second seal ring region around the second integrated circuit region, and a second alignment mark within the second seal ring region and corresponding to the first alignment mark,
- wherein the first alignment mark is between metal features of a first interconnect structure of the first die, and the second alignment mark is outside of metal features of a second interconnect structure of the second die.
A three-dimensional integrated circuit structure, comprising:
- a first die comprising a first integrated circuit region, a first seal ring region around the first integrated circuit region, and a first alignment mark within the first integrated circuit region;
- a second die bonded to the first die, comprising a second integrated circuit region, a second seal ring region around the second integrated circuit region, and a second alignment mark within the second seal ring region and corresponding to the first alignment mark;
- and
- a plurality of through dielectric vias over the first die and surrounding the second die,
- wherein the first die further comprises a plurality of first seal ring patterns at an outer side of the through dielectric vias.
Dependencies are inferred from the claim text.