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US 10,504,850 B2Granted
Semiconductor processing method
AssigneePep Innovation Pte. Ltd.
InventorYi Xin Chew
Life of this patent
Estimating the term…
Abstract
A semiconductor processing method is provided. The method includes providing a first carrier (10). A first adhesive (18) is provided on the first carrier (10) and a plurality of semiconductor chips (20) is placed on the first adhesive (18). A second carrier (28) is provided. The second carrier (28) is provided with a plurality of chip receiving areas (32). The first and second carriers (10) and (28) are then brought together to attach the semiconductor chips (20) to respective ones of the chip receiving areas (32) on the second carrier (28). The first carrier (10) is then separated from the semiconductor chips (20).
Claims69
A semiconductor processing method, comprising:
- providing a first carrier, wherein the first carrier is provided with a plurality of first global marks:
- providing the first carrier with a plurality of first unit marks, the first unit marks defining a plurality of chip placement positions;
- providing a first adhesive on the first carrier;
- aligning a plurality of chip marks on each of a plurality of semiconductor chips with corresponding ones of the first unit marks wherein the chip marks are provided on an active surface of the semiconductor chips;
- placing respective ones of the semiconductor chips on the first adhesive;
- providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks;
- aligning the first global marks with corresponding ones of the second global marks;
- bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier;
- and
- separating the first carrier from the semiconductor chips.
7 more elements
A semiconductor processing method, comprising:
- providing a first carrier, wherein the first carrier is provided with a plurality of first global marks;
- providing a first adhesive on the first carrier;
- placing a plurality of semiconductor chips on the first adhesive;
- providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks, and wherein the chip receiving areas comprise a plurality of chip pads provided on the second carrier;
- forming a plurality of second unit marks on one of a surface of the second carrier adjacent respective ones of the chip pads and the chip pads themselves;
- aligning the first global marks with corresponding ones of the second global marks;
- bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier;
- and
- separating the first carrier from the semiconductor chips.
6 more elements
A semiconductor processing method, comprising:
- providing a first carrier, wherein the first carrier is provided with a plurality of first global marks;
- providing a first adhesive on the first carrier;
- placing a plurality of semiconductor chips on the first adhesive;
- providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks;
- forming a dielectric layer on the second carrier, the dielectric layer encapsulating the semiconductor chips;
- determining a position of a plurality of terminal pads on each of the semiconductor chips based on a position of the second global marks;
- forming a plurality of openings in the dielectric layer to expose respective ones of the terminal pads;
- aligning the first global marks with corresponding ones of the second global marks;
- bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier;
- and
- separating the first carrier from the semiconductor chips.
8 more elements
A semiconductor processing method, comprising:
- providing a first carrier, wherein the first carrier is provided with a plurality of first global marks;
- providing a first adhesive on the first carrier;
- placing a plurality of semiconductor chips on the first adhesive;
- providing a second carrier, wherein the second carrier is provided with a plurality of chip receiving areas and a plurality of second global marks;
- forming a dielectric layer on the second carrier, the dielectric layer encapsulating the semiconductor chips;
- forming a plurality of openings in the dielectric layer to expose respective ones of the second global marks;
- aligning the first global marks with corresponding ones of the second global marks;
- bringing the first and second carriers together to attach the semiconductor chips to respective ones of the chip receiving areas on the second carrier;
- and
- separating the first carrier from the semiconductor chips.
7 more elements
Dependencies are inferred from the claim text.