Chip package structure and chip package structure array

A chip package structure array, comprising:

• a plurality of chip package structures, adapted to be arranged in array and form the chip package structure array, each of the chip package structures comprises:
• a plurality of first chips, each of the first chips having a first active surface;
• a plurality of first conductive pillars, each of the first conductive pillars being disposed on the first active surface of the corresponding first chip;
• a second chip, having a second active surface, and the second chip is an one-side connect die;
• a plurality of second conductive pillars, each of the second conductive pillars is connected between the first active surface of the corresponding first chip and the second active surface of the corresponding second chip, the second chip is electrically connected to the first active surfaces of the first chips only through the second conductive pillars, and a height of the first conductive pillars with respect to the first active surface is larger than a height of the second chip and the second conductive pillars with respect to the first active surface;
• an encapsulated material, covering the first chips, the second chip and the second conductive pillars, and partially covering the first conductive pillars;
• and
• a redistribution structure, disposed on the encapsulated material and connecting with the first conductive pillars, wherein a part of the encapsulated material is located between the second chip and the redistribution structure.