Three-dimensional semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-woo Kim, Joon-sung Lim, Jang-gn Yun, Sung-min Hwang
Life of this patent
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Abstract
A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.
Claims17
A three-dimensional (3D) semiconductor device, comprising:
- a substrate having a cell array region and a peripheral circuit region;
- a cell array structure in the cell array region and including a 3D memory cell array;
- a peripheral logic structure in the peripheral circuit region and including a peripheral circuit transistor;
- a cell insulating layer to insulate the cell array structure;
- and
- a peripheral insulating layer for insulating the peripheral logic structure from the cell array region, wherein
- the peripheral insulating layer includes:
- a silicon oxide layer covering the peripheral circuit transistor,
- a low dielectric layer on the silicon oxide layer and having a lower dielectric constant than the silicon oxide layer, and
- a porous layer on the low dielectric layer.
A three-dimensional (3D) semiconductor device, comprising:
- a substrate having a cell array region and a peripheral circuit region;
- a cell array structure in the cell array region and including a 3D memory cell array;
- a peripheral logic structure in the peripheral circuit region and including a peripheral circuit transistor;
- a cell insulating layer to insulate the cell array structure;
- and
- a peripheral insulating layer insulated from the peripheral logic structure and the cell array region and having a porous layer, wherein the peripheral insulating layer includes:
- a peripheral lower insulating layer on the peripheral circuit transistor,
- a peripheral upper insulating layer on the peripheral lower insulating layer, and
- a peripheral contact wiring structure electrically connected to the peripheral circuit transistor and in the peripheral insulating layer, and wherein the peripheral lower insulating layer includes:
- a first material layer on the peripheral circuit transistor and including a silicon oxide layer or a low dielectric layer having a lower dielectric constant than the silicon oxide, and
- a second material layer including a porous layer on the first material layer.
A three-dimensional (3D) semiconductor device, comprising:
- a substrate having a cell array region, a contact region, and a peripheral circuit region;
- a cell array structure in the cell array region and including a stacked structure and a vertical structure;
- a peripheral logic structure in the peripheral circuit region and including a peripheral circuit transistor;
- a contact wiring structure in the contact region and electrically connecting the cell array region and the peripheral circuit region;
- a cell insulating layer configured to insulate the cell array structure;
- a contact insulating layer to insulate the contact wiring structure;
- and
- a peripheral insulating layer that is insulated from the peripheral logic structure and the cell array region, the peripheral insulating layer including a low dielectric layer having a lower dielectric constant than a silicon oxide layer and a porous layer.
A three-dimensional (3D) semiconductor device, comprising:
- a first region including a 3D cell array;
- a second region including a peripheral logic structure;
- a first insulating layer in the second region and having a dielectric constant lower than silicon oxide, the first insulating layer between the peripheral logic structure and an area in the second region overlapping the peripheral logic structure;
- and
- a porous layer in the second region, wherein
- the porous layer has a hydrogen adsorption function.
Dependencies are inferred from the claim text.