Semiconductor device including a conductive feature over an active region

A semiconductor device comprising:

• a first gate structure over a substrate;
• a second gate structure over the substrate;
• an insulating layer over at least the first gate structure;
• a first conductive feature over and contacting a top surface of the second gate structure, wherein a topmost surface of the first conductive feature is coplanar with a topmost surface of the insulating layer;
• a second conductive feature over an active region of the substrate, wherein a portion of the first conductive feature is embedded in the second conductive feature, and wherein the topmost surface of the first conductive features is coplanar with a topmost surface of the second conductive feature;
• a pair of first spacers on each sidewall of the first gate structure;
• and
• a pair of second spacers on each sidewall of the second gate structure, the first conductive feature over and physically contacting one spacer of the pair of second spacers.

A semiconductor device comprising:

• a first gate structure and a second gate structure on a substrate;
• an active region in the substrate, the active region being between the first and second gate structures;
• a first insulating layer on the first gate structure and a second insulating layer on the second gate structure;
• a pair of first spacers on each sidewall of the first gate structure and one of the pair of first spacers on a sidewall of the first insulating layer;
• a pair of second spacers on each sidewall of the second gate structure and the second insulating layer;
• a first conductive feature between the first and second gate structures, the first conductive feature over and electrically coupled to the active region;
• a second conductive feature over at least the first gate structure, wherein a portion of a top surface of the second conductive feature is coplanar with a top surface of the second insulating layer over the second gate structure;
• and
• a third conductive feature over the substrate, wherein a top surface of the first conductive feature is coplanar with a top surface of the third conductive feature and a top surface of the first insulating layer on the first gate structure.