Device almost last embedded device structure and method of manufacturing thereof

A method of manufacturing an electronics package comprising:

• providing a pre-fabricated multilayer interconnect structure comprising a top surface and a bottom surface, the multilayer interconnect structure including:
• a plurality of insulating substrate layers each having a plurality of microvias formed therein;
• and
• a plurality of conductor layers positioned on the plurality of insulating substrate layers and in the plurality of microvias, the plurality of conductor layers comprising a plurality of first terminal pads positioned on the bottom surface of the multilayer interconnect structure;
• coupling an active surface of a semiconductor device to the bottom surface of the multilayer interconnect structure such that a plurality of semiconductor device first input/output (I/O) pads on the active surface are aligned to the plurality of first terminal pads;
• forming a plurality of through vias that extend from the top surface of the multilayer interconnect structure down to a plurality of semiconductor device second I/O pads on the active surface of the semiconductor device;
• and
• forming conductive through vias in the plurality of through vias that contact the plurality of semiconductor device second I/O pads.

An electronics package comprising:

• a multilayer interconnect structure comprising:
• a plurality of insulating substrate layers each comprising a plurality of microvias formed therein;
• and
• a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, with each of the plurality of insulating substrate layers having one or more conductive wiring layers positioned thereon;
• and
• a plurality of conductive microvias in the plurality of microvias to electrically connect the plurality of conductive wiring layers;
• wherein the plurality of conductive wiring layers and the plurality of conductive microvias are positioned in a perimeter region of the multilayer interconnect structure that surrounds a center region of the multilayer interconnect structure;
• and
• a semiconductor device attached to a bottom surface of the multilayer interconnect structure, the semiconductor device comprising a plurality of first input/output (I/O) pads aligned with the perimeter region and a plurality of second I/O pads aligned with the center region;
• and
• a plurality of conductive through vias extending through the multilayer interconnect structure in the center region and electrically connected to the plurality of second I/O pads.

A reconfigured semiconductor device comprising;

• a semiconductor device including a plurality of device I/O pads on an active surface thereof, the plurality of device I/O pads comprising first device I/O pads and second device I/O pads;
• a first redistribution layer on the active surface, the first redistribution layer comprising:
• a first insulating substrate layer;
• a first plurality of vias formed through the first insulating substrate layer to the plurality of device I/O pads;
• a first wiring layer overlying the first insulating substrate layer and extending into the plurality of vias down onto portions of the plurality of device I/O pads, the first wiring layer comprising a plurality of first contact pads connected to the plurality of device I/O pads;
• an upper redistribution layer overlying the first redistribution layer and comprising:
• an upper insulating substrate layer;
• a plurality of vias formed through the upper insulating substrate layer to a plurality of contact pads on a wiring layer below the upper insulating substrate layer, the wiring layer below the upper insulating substrate layer comprising the first wiring layer or an additional wiring layer between the first redistribution layer and the upper redistribution layer;
• and
• an upper wiring layer overlying the upper insulating substrate layer and extending into the plurality of vias and onto portions of the plurality contact pads on the wiring layer below the upper insulating substrate layer, the upper wiring layer comprising a plurality of upper contact pads connected to a plurality of contact pads on the wiring layer below the upper insulating substrate layer;
• wherein the upper contact pads comprise first reconfigured device I/O pads and second reconfigured device I/O pads, with each of a plurality of the first reconfigured device I/O pads electrically connected to a single respective first device I/O pad and each of a plurality of the second reconfigured device I/O pads electrically connected to at least two respective second device I/O pads.