Fan-out semiconductor package

A fan-out semiconductor package comprising:

• a frame including
• a plurality of insulating layers,
• a plurality of wiring layers disposed on the plurality of insulating layers, and
• a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and the frame having a recess portion having a bottom layer disposed on a bottom surface thereof;
• a semiconductor chip having
• connection pads,
• an active surface on which the connection pads are disposed, and
• an inactive surface opposing the active surface, and being disposed in the recess portion so that the inactive surface faces the bottom layer;
• first metal bumps disposed on the connection pads of the semiconductor chip;
• second metal bumps disposed on an uppermost wiring layer of the plurality of wiring layers;
• an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion, wherein an upper surface of the encapsulant is coplanar with upper surfaces of each of the first and second metal bumps;
• and
• a connection member including an insulating layer disposed on the coplanar upper surfaces of the encapsulant and first and second metal bumps to face the frame and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, and first and second connection vias penetrating through the insulating layer and integrated with the redistribution layer, the redistribution layer connected to the first and second metal bumps through the first and second connection vias, respectively.