Self-aligned nanowire formation using double patterning

A method comprising:

• forming a first amorphous silicon layer over a semiconductor substrate;
• forming a patterned second amorphous silicon layer over the first amorphous silicon layer;
• forming first spacers based on the patterned second amorphous silicon layer;
• removing the patterned second amorphous silicon layer;
• etching the first amorphous silicon layer using the first spacers as a first etching mask;
• forming a patterned third amorphous silicon layer over the first amorphous silicon layer;
• forming second spacers based on the patterned third amorphous silicon layer;
• removing the patterned third amorphous silicon layer;
• etching the first amorphous silicon layer using the second spacers as a second etching mask to form amorphous silicon nanowires;
• and
• transferring patterns of the amorphous silicon nanowires into the semiconductor substrate to form semiconductor nanowires.

A method comprising:

• forming amorphous silicon nanowires;
• rounding the amorphous silicon nanowires;
• transferring patterns of the rounded amorphous silicon nanowires into a semiconductor substrate underlying the rounded amorphous silicon nanowires to form semiconductor nanowires;
• and
• forming vertical transistors based on the semiconductor nanowires, with portions of the semiconductor nanowires acting as channel regions of the vertical transistors.