Memory device and operating method thereof

A memory device having a memory cell array including a plurality of memory banks, the memory device comprising:

• a page buffer group including a plurality of page buffer circuits respectively coupled to the plurality of memory banks, the plurality of page buffer circuits storing data to be stored in the plurality of memory banks and storing data read from the plurality of memory banks;
• and
• a BIST controller configured to test a data path of the memory device by performing a BIST write operation of storing pattern data in the plurality of page buffer circuits and performing a BIST read operation of reading data stored in the page buffer circuits,
• wherein the BIST controller includes:
• a reference clock generator configured to generate a reference clock having a preset target frequency;
• a BIST logic configured to, in response to a BIST enable signal input from an external test device, generate a data input enable signal in the BIST write operation and generate a data output enable signal in the BIST read operation;
• a clock timing controller configured to generate an input sample clock by using the data input enable signal and the reference clock in the BIST write operation;
• and
• a pattern data generator configured to generate the pattern data according to the input sample clock.

A method for operating a memory device, the method comprising:

• receiving a write command and a write address from an external device;
• generating pattern data to be stored in a page buffer circuit corresponding to the write address in response to the write command;
• storing the pattern data in the page buffer circuit corresponding to the write address;
• receiving a read command and a read address from the external device;
• generating the pattern data in response to the read command;
• and
• comparing the pattern data with sensed data obtained from the page buffer circuit,
• wherein the generating the pattern data includes:
• generating a reference clock having a preset target frequency;
• in response to a BIST enable signal input from an external test device, generating a data input enable signal in a BIST write operation and generate a data output enable signal in a BIST read operation;
• generating an input sample clock by using the data input enable signal and the reference clock in the BIST write operation;
• and
• generating the pattern data according to the input sample clock.