Apparatus configured to program memory cells using an intermediate level for multiple data states

A memory device, comprising:

• an array of memory cells;
• and
• a controller configured to cause the memory device to perform a method comprising:
• applying a particular programming pulse to an access line coupled to a grouping of memory cells of the array of memory cells during a write operation, wherein the grouping of memory cells comprises a plurality of subsets of memory cells, and wherein each subset of memory cells of the plurality of subsets of memory cells has a respective desired data state of a plurality of data states for the write operation;
• while applying the particular programming pulse to the access line, inhibiting memory cells of a first subset of memory cells of the plurality of subsets of memory cells from programming, partially inhibiting memory cells of a second subset of memory cells of the plurality of subsets of memory cells from programming, and enabling memory cells of a third subset of memory cells of the plurality of subsets of memory cells for programming;
• and
• after applying the particular programming pulse to the access line and without determining whether any memory cell of the plurality of subsets of memory cells has reached the respective desired data state for its respective subset of memory cells in response to applying the particular programming pulse to the access line, applying a subsequent programming pulse to the access line while inhibiting the memory cells of the particular subset of memory cells from programming and while enabling the memory cells of the second subset of memory cells and the third subset of memory cells for programming.

A memory device, comprising:

• an array of memory cells;
• and
• a controller configured to cause the memory device to perform a method comprising:
• applying a particular programming pulse to an access line coupled to a grouping of memory cells of the array of memory cells during a write operation, wherein the grouping of memory cells comprises a plurality of subsets of memory cells, and wherein each subset of memory cells of the plurality of subsets of memory cells has a respective desired data state of a plurality of data states for the write operation;
• while applying the particular programming pulse to the access line, inhibiting memory cells of a first subset of memory cells of the plurality of subsets of memory cells from programming, inhibiting memory cells of a second subset of memory cells of the plurality of subsets of memory cells from programming, enabling memory cells of a third subset of memory cells of the plurality of subsets of memory cells for programming, and enabling memory cells of a fourth subset of memory cells of the plurality of subsets of memory cells for programming;
• and
• after applying the particular programming pulse to the access line and without determining whether any memory cell of the plurality of subsets of memory cells has reached the respective desired data state for its respective subset of memory cells in response to applying the particular programming pulse to the access line, applying a subsequent programming pulse to the access line while inhibiting the memory cells of the first subset of memory cells from programming and while enabling the memory cells of the second subset of memory cells, the third subset of memory cells and the fourth subset of memory cells for programming;
• wherein the respective desired data state of the first subset of memory cells corresponds to a first range of threshold voltages;
• wherein the respective desired data state of the second subset of memory cells corresponds to a second range of threshold voltages higher than the first range of threshold voltages;
• wherein the respective desired data state of the third subset of memory cells corresponds to a third range of threshold voltages higher than the second range of threshold voltages;
• and
• wherein the respective desired data state of the fourth subset of memory cells corresponds to a fourth range of threshold voltages higher than the third range of threshold voltages.