Non-volatile semiconductor storage device with two write modes

A non-volatile semiconductor storage device comprising:

• a memory cell array that includes a plurality of non-volatile memory cells that are connected to a plurality of bit lines and a plurality of word lines;
• a control circuit configured to control a data write operation for the memory cell array in one of first and second write modes in response to a write command sequence;
• an input/output circuit;
• and
• a data buffer that is connected to the input/output circuit via a data path, wherein
• in the first write mode, the control circuit performs a first write operation, which includes an operation in which one or more bit lines of the plurality of bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line of the plurality of word lines selected according to address data included in the write command sequence, and
• in the second write mode, the control circuit performs a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line, and
• during the second write operation, the control circuit loads first data to the data buffer, transmits data from the data buffer to an internal register via the data path, returns data from the internal register to the data buffer via the data path, and sets a result of comparing the data returned to the data buffer with the first data in a status register.

A method of operating a non-volatile semiconductor storage device having a memory cell array that includes a plurality of non-volatile memory cells that are connected to a plurality of bit lines and a plurality of word lines in one of a first write mode and a second write mode in response to a write command sequence, said method comprising:

• setting the non-volatile semiconductor storage device in a first write mode or a second write mode in response to a set feature command sequence;
• while in the first write mode, in response to the write command sequence, performing a first write operation, which includes a first operation in which one or more bit lines of the plurality of bit lines are charged according to write data, a second operation in which a write voltage is applied to a selected word line of the plurality of word lines selected according to address data included in the write command sequence, and a third operation in which the plurality of bit lines are reset, the third operation beginning immediately after the second operation ends, and
• while in the second write mode, in response to the write command sequence, performing a second write operation, which includes the first operation in which the one or more bit lines are charged according to the write data and the third operation in which the plurality of bit lines are reset, the third operation beginning immediately after the first operation ends, and wherein the second write mode does not include the second operation in which the write voltage is applied to the selected word line.

A method of operating a non-volatile semiconductor storage device having a memory cell array that includes a plurality of non-volatile memory cells that are connected to a plurality of bit lines, a plurality of word lines in one of a first write mode and a second write mode in response to a write command sequence, an input/output circuit, and a data buffer that is connected to the input/output circuit via a data path, the method comprising:

• setting the non-volatile semiconductor storage device in a first write mode or a second write mode in response to a set feature command sequence;
• while in the first write mode, in response to the write command sequence, performing a first write operation, which includes an operation in which one or more bit lines of the plurality of bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line of the plurality of word lines selected according to address data included in the write command sequence;
• and
• while in the second write mode, in response to the write command sequence, performing a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line;
• and
• during the second write operation, loading first data to the data buffer, transmitting data from the data buffer to an internal register via the data path, returning data from the internal register to the data buffer via the data path, and setting a result of comparing the data returned to the data buffer with the first data in a status register.