Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsTakuya Futatsuyama, Masanobu Shirakawa
Life of this patent
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Abstract
A semiconductor memory device according to an embodiment includes: first to 32nd memory cells; first to 16th bit lines connected to the first to 16th memory cells; 17th to 32nd bit lines connected to the 17th to 32nd memory cells; a first word line connected to gates of the first to 32nd memory cells; first to 16th sense amplifiers configured to determine data read from the first to 16th memory cells at a first timing; and 17th to 32nd sense amplifiers configured to determine data read from the 17th to 32nd memory cells at a second timing. The first timing is different from the second timing.
Claims6
A semiconductor memory device having a first read mode and a second read mode, comprising:
- a first memory cell and a second memory cell;
- a first word line connected to a gate of the first memory cell and a gate of the second memory cell;
- a first bit line connected to the first memory cell;
- a second bit line connected to the second memory cell;
- a first sense amplifier configured to determine data read from the first memory cell at a first timing in the first and second read modes;
- a second sense amplifier configured to determine data read from the second memory cell at a second timing different from the first timing in the first read mode, and to determine the data at the first timing in the second read mode;
- and
- a delay circuit configured to generate a second signal by delaying a first signal in the first read mode;
- wherein in the first read mode, a voltage of the first word line is continuously raised, and in the second read mode, the voltage of the first word line is stepped up;
- wherein in the second read mode, the first sense amplifier determines the data based on the first signal, and the second sense amplifier determines the data based on the second signal;
- and
- wherein the semiconductor memory device further comprises a controller configured to:
- upon receipt of a first command set, supply the second signal to the second sense amplifier with a delay with respect to the first signal supplied to the first sense amplifier, thereby executing a read operation on the first memory cell and the second memory cell in the first read mode, and
- upon receipt of a second command set, supply the second signal to the second sense amplifier without the delay with respect to the first signal supplied to the first sense amplifier, thereby executing a read operation on the first memory cell and the second memory cell in the second read mode.
Dependencies are inferred from the claim text.