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US 10,504,592 B2Granted
Systems, methods and devices for programming a multilevel resistive memory cell
AssigneeMicron Technology, Inc.
InventorsPaolo Fantini, Massimo Ferro
Life of this patent
Estimating the term…
Abstract
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.
Claims20
A method, comprising:
- applying one or more first reverse-biased electrical pulses to a memory cell;
- programming the memory cell from a first programming state to a reset programming state based at least in part on applying the one or more first reverse-biased electrical pulses;
- applying one or more second reverse-biased electrical pulses to the memory cell;
- and
- programming the memory cell from the reset programming state to the first programming state based at least in part on applying the one or more second reverse-biased electrical pulses.
2 more elements
A method, comprising:
- applying one or more first reverse-biased electrical pulses to a memory cell;
- programming the memory cell from a first programming state to a reset programming state based at least in part on applying the one or more first reverse-biased electrical pulses;
- applying one or more first forward-biased electrical pulses to the memory cell;
- and
- programming the memory cell from the reset programming state to a set programming state based at least in part on applying the one or more first forward-biased electrical pulses, wherein the one or more first forward-biased electrical pulses sequentially ramp in a falling staircase sequence.
2 more elements
A memory device, comprising:
- a memory array comprising a plurality of memory cells;
- and
- a control unit configured to:
- program one or more memory cells of the plurality of memory cells from a first programming state to a reset programming state based at least in part on applying one or more first reverse-biased electrical pulses;
- and
- program the one or more memory cells from the reset programming state to the first programming state based at least in part on applying one or more second reverse-biased electrical pulses.
3 more elements
A memory device, comprising
- a memory array comprising a plurality of memory cells;
- and
- a control unit configured to:
- program one or more memory cells of the plurality of memory cells from a first programming state to a reset programming state based at least in part on applying one or more first reverse-biased electrical pulses;
- and
- program the one or more memory cells from the reset programming state to a set programming state based at least in part on applying one or more first forward-biased electrical pulses that sequentially ramp in a decreasing sequence to the one or more memory cells.
3 more elements
Dependencies are inferred from the claim text.