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US 10,504,586 B2Granted
Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorYasuhiro Shiino
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory device includes memory cells, a word line, bit lines, and a controller. The word line is connected to the memory cells. Each of the lines is connected to the memory cells. In a program operation, while applying a program voltage to the word line, the controller applies a first voltage to a bit line connected to memory cells to which a first data is to be written, applies a second voltage lower than the first voltage to a bit line connected to memory cells to which a second data is to be written, and applies a third voltage lower than the second voltage to a bit line connected to memory cells to which a third data is to be written.
Claims20
A semiconductor memory device comprising:
- a plurality of memory cells which include a first memory cell, a second memory cell, and a third memory cell, each configured to store a plurality of bits of data based on a threshold voltage and to be set to have a first threshold voltage in a case of storing first data as the plurality of bits of data, set to have a second threshold voltage higher than the first threshold voltage in a case of storing second data as the plurality of bits of data, and set to have a third threshold voltage higher than the second threshold voltage in a case of storing third data as the plurality of bits of data;
- a word line connected to a plurality of the memory cells;
- a plurality of bit lines which include a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, and a third bit line connected to the third memory cell;
- and
- a controller configured to perform a write operation including a plurality of program loops each including a program operation and a verify operation, wherein
- the controller applies a first program voltage to the word line in the program operation in a first program loop included in the program loops, and
- while applying the first program voltage,
- applies a first voltage to the first bit line connected to memory cell to which the first data is to be written,
- applies a second voltage lower than the first voltage to the second bit line connected to the second memory cell to which the second data is to be written, and
- applies a third voltage lower than the second voltage to the third bit line connected to the third memory cell to which the third data is to be written, wherein
- the controller applies, in the verify operation, a first verify voltage to the word line, and
- while applying the first verify voltage in the verify operation in the first program loop,
- applies a fourth voltage to the first bit line connected to the first memory cell to which the first data is to be written,
- applies a fifth voltage which is different from the fourth voltage to the second bit line connected to the second memory cell to which the second data is to be written, and
- applies a sixth voltage which is different from the fourth voltage and the fifth voltage to the third bit line connected to the third memory cell to which the third data is to be written, wherein
- the verify operation is executed for the first memory cell, the second memory cell, and the third memory cell concurrently.
13 more elements
A semiconductor memory device comprising:
- a plurality of memory cells which include a first memory cell, a second memory cell, and a third memory cell, each configured to store a plurality of bits of data based on a threshold voltage and to be set to have a first threshold voltage in a case of storing first data as the plurality of bits of data, set to have a second threshold voltage higher than the first threshold voltage in a case of storing second data as the plurality of bits of data, and set to have a third threshold voltage higher than the second threshold voltage in a case of storing third data as the plurality of bits of data;
- a word line connected to a plurality of the memory cells;
- a plurality of bit lines which include a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, and a third bit line connected to the third memory cell;
- and
- a controller configured to perform a write operation including a plurality of program loops, each including a program operation and a verify operation, the controller configured to apply a first voltage to the first bit line, a second voltage to the second bit line, and a third voltage to the third bit line in the program operation in a first program loop included in the program loops,
- in the verify operation, apply a verify voltage to the word line, and
- while applying the verify voltage in the verify operation in the first program loop, apply a fourth voltage to the first bit line connected to the first memory cell to which the first data is to be written, apply a fifth voltage which is different from the fourth voltage to the second bit line connected to the second memory cell to which the second data is to be written, and apply a sixth voltage which is different from the fourth voltage and the fifth voltage to the third bit line connected to the third memory cell to which the third data is to be written, wherein
- the verify operation to the first memory cell, the second memory cell, and the third memory cell is executed concurrently.
5 more elements
Dependencies are inferred from the claim text.