Directed per bank refresh command

A computing system, comprising:

• a plurality of processing cores;
• a network interface;
• a memory;
• a memory controller coupled to the memory;
• and,
• first counter logic circuitry and second counter logic circuitry to manage refresh commands of a memory device, the first counter logic circuitry to increment a first counter value in response to an all bank refresh command being issued to the memory device, the second counter logic circuitry to increment a second counter value in response to a single bank refresh command being issued to the memory device, the second counter logic circuitry to reset the second counter value in response to the all bank refresh command being issued to the memory device, the first counter logic circuitry to increment the first counter value and the second counter logic circuitry to roll over the second counter value in response to a separate single bank refresh command being issued for each bank of the memory device while the first counter value remains at a same value.

A method, comprising:

• managing refresh commands of a memory device by performing the following with first counter logic circuitry and second counter logic circuitry:
• with the first counter logic circuitry, incrementing a first counter value in response to an all bank refresh command being issued to the memory device;
• with the second counter logic circuitry, incrementing a second counter value in response to a single bank refresh command being issued to the memory device and resetting the second counter value in response to the all bank refresh command being issued to the memory device;
• with the first counter logic circuitry, incrementing the first counter value and the second counter logic circuitry to roll over the second counter value in response to a separate single bank refresh command being issued for each bank of the memory device while the first counter value remains at a same value.