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US 10,504,577 B1Granted
Apparatus with a row hit rate/refresh management mechanism
AssigneeMicron Technology, Inc.
InventorJoshua E. Alzheimer
Life of this patent
Estimating the term…
Abstract
The apparatus includes: a row hammer refresh (RHR) circuit configured to: steal a first stolen cycle to implement an RHR operation or a portion thereof, and steal a second stolen cycle after one or more operating cycles, the second stolen cycle to implement the RHR operation or a different portion thereof.
Claims20
An apparatus, comprising:
- a row hammer refresh (RHR) circuit configured to:
- receive a command to perform a refresh operation on a portion of a memory array,
- steal a first stolen cycle of the refresh operation to implement a first portion of a RHR operation, and
- steal a second stolen cycle of the refresh operation to implement a second portion of the RHR operation, the second stolen cycle being subsequent to and non-adjacent to the first stolen cycle;
- and
- a memory array operably coupled to the RHR circuit, the memory array configured to:
- implement the first portion of the RHR operation during the first stolen cycle,
- implement the refresh operation or a portion thereof after the first stolen cycle, and
- implement the second portion of the RHR operation during the second stolen cycle after implementing the refresh operation or a portion thereof.
6 more elements
A method of operating an apparatus, the method comprising:
- stealing a first stolen cycle of an overall memory refresh sequence that refreshes charges stored at specific locations in a memory array, the first stolen cycle to implementing a first portion of a row hammer refresh (RHR) operation;
- delaying one or more operating cycles to implement a scheduled refresh operation or a portion thereof during the one or more operating cycles following the first stolen cycle;
- and
- stealing a second stolen cycle after the one or more operating cycles, the second stolen cycle to implement the second portion of the RHR operation.
1 more element
An apparatus, comprising:
- a row hammer refresh (RHR) circuit configured to:
- steal a first stolen cycle to implement an RHR operation or a portion thereof, and
- steal a second stolen cycle after one or more operating cycles, the second stolen cycle to implement the RHR operation or a different portion thereof;
- and
- an address adjuster circuit operably coupled to the RHR circuit, the address adjuster circuit configured to:
- receive a refresh address corresponding to a location of the memory array associated with a scheduled refresh operation, wherein at least a portion of the scheduled refresh operation corresponds to the one or more operating cycles between the first stolen cycle and the second stolen cycle;
- receive an RHR address corresponding to a different location of the memory array associated with the RHR operation;
- and
- generate an adjusted address based on the refresh address and the RHR address, the adjusted address to replace the refresh address for one or more operating cycles.
6 more elements
Dependencies are inferred from the claim text.