Methods for addressing high capacity SDRAM-like memory without increasing pin cost

A method for addressing data in a memory device, the data being arranged in an array of rows and columns respectively indexed by a first number of row address bits and a second number of column address bits, the data being addressed using an architecture defined by a row address command specifying a third number of row address bits followed by a column address command specifying a fourth number of column address bits, the second number being greater than the fourth number, the method comprising:

• splitting the second number of column address bits into a third subset of column address bits and a fourth subset of column address bits;
• specifying the fourth subset in the column address command and the third subset in a previous address command when the second number is greater than the fourth number;
• and
• processing the column address command as all or part of a column access command corresponding to a row.

A memory device comprising:

• storage cells for storing data arranged in an array of rows and columns respectively indexed by a first number of row address bits and a second number of column address bits,
• wherein the data in the memory device is addressed using an architecture defined by a row address command specifying a third number of row address bits followed by a column address command specifying a fourth number of column address bits, the first number being greater than the third number, and
• wherein the memory device is configured to address the data by:
• splitting the first number of row address bits into a first subset of row address bits and a second subset of row address bits, and specifying the first subset in the row address command and the second subset in a next address command when the first number is greater than the third number;
• and
• processing the row address command as all or part of a row access of a row of the memory device.