Semiconductor device and timing calibration method
AssigneeRenesas Electronics Corporation
InventorTakayuki Hotaruhara
Life of this patent
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Abstract
When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded. A delay adjustment circuit adjusts a delay amount of write data to a memory device. A control circuit sets a delay amount of the delay adjustment circuit. A storage unit stores a delay amount. The control circuit corrects the delay amount stored in the storage unit based on a writing result of write data obtained when the delay amount stored in the storage unit or an amount based on that delay amount is set on the delay adjustment circuit.
Claims17
A semiconductor device comprising:
- a delay adjustment circuit for adjusting a delay amount in writing of write data or a data strobe signal to a memory device;
- a control circuit for setting the delay amount of the delay adjustment circuit;
- and
- a storage unit storing the delay amount,
- wherein during a first adjustment period, the control circuit determines a first delay amount as the delay amount of the delay adjustment circuit for a timing of a left edge of an effective window of the write data to meet a timing of an edge of the data strobe signal, determines a second delay amount as the delay amount of the delay adjustment circuit for a timing of a right edge of an effective window of the write data to meet the timing of an edge of the data strobe signal, determines a third delay amount as an average value of the first delay amount and the second delay amount, and writes the first delay amount, the second delay amount, and the third delay amount to the storage unit,
- wherein in normal operation, the control circuit sets the third delay amount stored in the storage unit as the delay amount of the delay adjustment circuit, and
- wherein during a second adjustment period provided after the first adjustment period, the control circuit corrects at least one of the first delay amount, the second delay amount, and the third delay amount stored in the storage unit or none of them based on a writing result of the write data obtained when the first delay amount stored in the storage unit is set as the delay amount of the delay adjustment circuit and a writing result of the write data obtained when the second delay amount stored in the storage unit is set as the delay amount of the delay adjustment circuit.
A semiconductor device comprising:
- a delay adjustment circuit for adjusting a delay amount in writing of write data or a data strobe signal to a memory device;
- a control circuit for setting the delay amount of the delay adjustment circuit;
- and
- a storage unit storing the delay amount,
- wherein during a first adjustment period, the control circuit determines a first delay amount as the delay amount of the delay adjustment circuit for a timing of a left edge of an effective window of the write data to meet a timing of an edge of the data strobe signal, determines a second delay amount as the delay amount of the delay adjustment circuit for a timing of a right edge of an effective window of the write data to meet the timing of an edge of the data strobe signal, determines as a third delay amount an average value of the first delay amount and the second delay amount, and writes the first delay amount, the second delay amount, and the third delay amount to the storage unit,
- wherein in normal operation, the control circuit sets the third delay amount stored in the storage unit as the delay amount of the delay adjustment circuit, and
- wherein during a second adjustment period provided after the first adjustment period, the control circuit corrects at least one of the first delay amount, the second delay amount, and the third delay amount stored in the storage unit or none of them based on at least a comparing result of the write data written into the memory device with read data read from the memory device after the delay amount larger than the first delay amount stored in the storage unit by a predetermined amount is set as the delay amount of the delay adjustment circuit and a comparing result of the write data written into the memory device with read data read from the memory device after the delay amount smaller than the second delay amount stored in the storage unit by the predetermined amount is set as the delay amount of the delay adjustment circuit.
A timing calibration method in which a delay adjustment circuit adjusting a delay amount in writing of write data or a data strobe signal to a memory device is used to calibrate the relation in timing between write data and a data strobe signal to the memory device, the timing calibration method comprising:
- during a first adjustment period, determining a first delay amount as the delay amount of the delay adjustment circuit for a timing of a left edge of an effective window of the write data to meet a timing of an edge of the data strobe signal, determining a second delay amount as the delay amount of the delay adjustment circuit for a timing of a right edge of an effective window of the write data to meet the timing of an edge of the data strobe signal, determining a third delay amount as an average value of the first delay amount and the second delay amount, and writing the first delay amount, the second delay amount, and the third delay amount to a storage unit,
- in normal operation, setting the third delay amount stored in the storage unit as the delay amount of the delay adjustment circuit, and
- during a second adjustment period provided after the first adjustment period, correcting at least one of the first delay amount, the second delay amount, and the third delay amount stored in the storage unit or none of them based on a comparing result of the write data written into the memory device with read data read from the memory device after the first delay amount stored in the storage unit is set as the delay amount of the delay adjustment circuit and based on a comparing result of the write data written into the memory device with read data read from the memory device of the write data after the second delay amount stored in the storage unit is set as the delay amount of the delay adjustment circuit.
Dependencies are inferred from the claim text.