System and method for controlling phase alignment of clock signals

A circuitry for controlling phase alignment of clock signals, said circuitry comprising:

• a first delay circuit, said delay circuit receiving a clock signal, said delay circuit further configured to transmit said clock signal to a phase detection circuit;
• a phase detection circuit, said phase detection circuit configured to receive said clock signal from the first delay circuit, and a calibration data signal from a synchronizing circuit, as inputs thereto, said phase detection circuit further configured to determine whether there exists a phase difference between said clock signal and said calibration data signal, said phase detection circuit further configured to generate a calibration output signal based on phase difference between clock signal and said calibration data signal;
• and
• a controllable delay circuit, said controllable delay circuit configured to receive said calibration output signal, said controllable delay circuit configured to iteratively calibrate a delay corresponding thereto, based on the calibration output signal received from said phase detection circuit until the clock signal and the calibration data signal are determined to be in phase, said controllable delay circuit further configured to determine a delay value that brought the clock signal in phase with the calibration data signal, and delay the clock signal transmitted there from at least by said delay value such that the clock signal transmitted from said controllable delay circuit is in phase with the clock signal transmitted to said first delay circuit;
• wherein said synchronizing circuit includes at least two flip-flops arranged in parallel, and wherein at least one of said flip-flops is configured to capture the clock signal output from said controllable delay circuit, said flip-flop further configured to generate the calibration data signal based on captured clock signal.