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US 10,504,479 B2Granted
Display device
AssigneeInnolux Corporation
InventorMasahiro Yoshiga
Life of this patent
Estimating the term…
Abstract
The display panel includes a source line, a common voltage line, a gate line, and a pixel circuit. The pixel circuit includes a first capacitor, a first transistor, a sample circuit, and a memory circuit. The first capacitor is coupled to the common voltage line. The first transistor is coupled to the source line and the first capacitor. The sample circuit includes a second transistor, and the second transistor is coupled to the source line and the first capacitor. The memory circuit is coupled to the first transistor, the sample circuit, and the gate line.
Claims16
A display device comprising:
- a display panel comprising:
- a source line;
- a common voltage line;
- a first control line;
- a second control line;
- a third control line;
- a gate line;
- and
- a pixel circuit comprising:
- a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the common voltage line;
- a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the source line, and the second terminal of the first transistor is coupled to the second terminal of the first capacitor;
- a sample circuit comprising:
- a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the source line, and the control terminal of the second transistor is coupled to the second terminal of the first capacitor;
- and
- a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth transistor is coupled to the second terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the second control line;
- and
- a memory circuit comprising:
- a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the first control line;
- a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor, the second terminal of the third transistor is coupled to the gate line, and the control terminal of the third transistor is coupled to the second terminal of the second capacitor and the first terminal of the fourth transistor;
- and
- a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the third control line, and the second terminal of the third capacitor is coupled to the control terminal of the first transistor.
18 more elements
A display panel comprising:
- a source line;
- a common voltage line;
- a first control line;
- a second control line;
- a third control line;
- a gate line;
- and
- a pixel circuit comprising:
- a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the common voltage line;
- a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the source line, and the second terminal of the first transistor is coupled to the second terminal of the first capacitor;
- a sample circuit coupled to the second terminal of the first capacitor and comprising:
- a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the source line, and the control terminal of the second transistor is coupled to the second terminal of the first capacitor;
- and
- a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth transistor is coupled to the second terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the second control line;
- and
- a memory circuit comprising:
- a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the first control line;
- a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor, the second terminal of the third transistor is coupled to the gate line, and the control terminal of the third transistor is coupled to the second terminal of the second capacitor and the first terminal of the fourth transistor;
- and
- a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the third control line, and the second terminal of the third capacitor is coupled to the control terminal of the first transistor.
17 more elements
Dependencies are inferred from the claim text.