Half-power buffer and/or amplifier

A half-power buffer and/or amplifier comprising:

• an amplifying unit configured to amplify a differential input signal, the amplifying unit comprising first to fourth nodes configured to output first to fourth outputs;
• a first output buffer unit comprising first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and a first output node configured to connect the first and second transistors, the first transistor having a gate connected to the first node, the second transistor having a gate connected to the second node;
• a second output buffer unit comprising third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and a second output node configured to connect the third and fourth transistors, the third and fourth transistors having gates connected to corresponding ones of the third and fourth nodes, respectively, the second output node being configured to output a voltage over a second voltage range between the second voltage and the third voltage;
• a first charge share switch unit connected between the gate of the second transistor and the first voltage source;
• a first output switch unit comprising a seventh switch (i) connected between the first node and the gate of the first transistor and (ii) configured to receive a third control signal, an eighth switch (iii) connected between the second voltage source and the gate of the second transistor and (iv) configured to receive a fourth control signal, and a ninth switch (v) connected between the first voltage source and the gate of the first transistor and (vi) configured to receive a fifth control signal;
• a second charge share switch unit connected between the gate of the third transistor and the second voltage source;
• a second output switch unit comprising (i) a tenth switch connected between the fourth node and the gate of the fourth transistor and (ii) configured to receive the fourth control signal, an eleventh switch (iii) connected between the first voltage source and the gate of the third transistor and (iv) configured to receive the third control signal, and a twelfth switch (v) connected between the second voltage source and the gate of the fourth transistor and (vi) configured to receive a sixth control signal;
• and
• a third output node configured to connect the first and second output nodes,
• wherein:
• the first output buffer unit outputs a first output voltage over a first voltage range between the first voltage and the third voltage on the third output node in a first operation period;
• the second output buffer unit outputs a voltage over a second voltage range between the second voltage and the third voltage on the third output node in a second operation period;
• the first and second charge share switch units control the second and third transistors and/or equilibrate a voltage at the third output node with the third voltage in a third operation period between the first operation period and the second operation period,
• the first charge share switch unit comprises first and second switches connected between the first voltage source and the gate of the second transistor and a third switch connected between the second node and the gate of the second transistor,
• the second charge share switch unit comprises fourth and fifth switches connected between the second voltage source and the gate of the third transistor,
• the first and second switches provide the first voltage of the first voltage source to the gate of the second transistor in response to the first control signal,
• the fourth and fifth switches provide the second voltage of the second voltage source to the gate of the third transistor in response to the first control signal,
• the eighth switch provides the second voltage of the second voltage source to the gate of the second transistor in response to the fourth control signal, and
• the eleventh switch provides the first voltage of the first voltage source to the gate of the third transistor in response to the third control signal.