Driving apparatus, display apparatus with output enable signal driving circuit and driving method thereof

A driving apparatus comprising a gate driving circuit, a source driving circuit and an output enable signal driving circuit, wherein:

• the gate driving circuit, which is connected to each of gate lines, is configured to input a gate driving signal to one of the gate lines during each scan cycle;
• the source driving circuit, which is connected to each of data lines, is configured to input a data signal to each of data lines during each scan cycle and invert the polarities of the data signal input to the same data line every preset number of scan cycles;
• and
• the output enable signal driving circuit, which is connected to an output enable signal line, is configured to input a voltage signal having a first duration to the output enable signal line in response to the condition that the polarities of the data signal are inverted during a first scan cycle, and input a voltage signal having a second duration longer than the first duration to the output enable signal line in response to the condition that the polarities of the data signal are not inverted during a second scan cycle, the sum of the first duration and the turn-on duration of a first gate line which is turned on during the first scan cycle substantially matches the sum of the second duration and the turn-on duration of a second gate line which is turned on during the second scan cycle;
• wherein the first gate line is switched off at a rising edge of an output enable signal and the second gate line is turned on at a falling edge of the output enable signal;
• wherein the first gate line is an odd gate line in a dual-gate structure, and the second gate line is an even gate line in the dual-gate structure;
• wherein the turn-on duration of the first gate line is more than the turn-on duration of the second gate line;
• wherein the turn-on duration of the first gate line is configured for all odd gate lines, and the turn-on duration of the second gate line is configured for all even gate lines;
• and
• wherein the first scan cycle is for the odd gate line, and the second scan cycle is for the even gate line.