Pixel internal compensation circuit and driving method

A pixel internal compensation circuit, which comprises:

• a first thin film transistor (TFT), having a gate connected to a third control signal, a source and a drain connected respectively to a data voltage and a first node;
• a second TFT, having a gate connected to the first node, a source and a drain connected respectively to a second node and a high voltage power source;
• a third TFT, having a gate connected to a first control signal, a source and a drain connected respectively to the first node and a reference voltage;
• a fourth TFT, having a gate connected to a second control signal, a source and a drain connected respectively to the second node and an initial voltage;
• a capacitor, having two ends connected respectively to the first node and the second node;
• an OLED, having an anode connected to the second node, and a cathode connected to a low voltage power source;
• wherein the initial voltage is less than activation voltage of the OLED, and the difference between reference voltage and initial voltage (reference voltage−initial voltage) is greater than threshold voltage of the second TFT;
• wherein the first control signal, the second control signal, and the third control signal have timing sequence configured for a reset phase, a sensing phase, a data write-in phase, and a light-emitting phase;
• wherein in the reset phase, the first control signal is at high voltage, the second control signal is at high voltage, and the third control signal is at low voltage;
• wherein in the sensing phase, the first control signal is at high voltage, the second control signal is at low voltage, and the third control signal is at low voltage;
• wherein in the data write-in phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at high voltage;
• and
• wherein the first control signal, the second control signal, and the third control signal of pixels of a current row and the first control signal, the second control signal, and the third control signal of pixels of an adjacent row are configured so that the data write-in phase of the pixels of the current row and the data write-in phase of the pixels of the adjacent row do not overlap, and the reset phase and the sensing phase of the pixels of the current row respectively overlap the reset phase and the sensing phase of the pixels of the adjacent row.