Display apparatus and method of driving the same

A display apparatus comprising:

• a display panel comprising a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines;
• a scan driver configured to sequentially output a plurality of scan signals to the plurality of scan lines;
• a first data driver circuit configured to sequentially output a plurality of first data signals to the plurality of first data lines;
• a second data driver circuit configured to sequentially output a plurality of second data signals to the plurality of second data lines based on a feedback signal received from the first data driver circuit;
• and
• a timing controller,
• wherein each of the first and second data driver circuits comprises a plurality of output channels, and the timing controller is configured to provide each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among the plurality of output channels, and
• wherein the first data driver circuit is configured:
• to generate a first internal clock signal based on an external clock signal,
• to sequentially output a plurality of first data signals based on the first internal clock signal and the delay difference,
• to generate a second internal clock signal delayed from the first internal clock signal based on the delay difference, and
• to output the feedback signal as the second internal clock signal.

A method of driving a display apparatus that comprises a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the method comprising:

• outputting a scan signal to the plurality of scan lines;
• sequentially outputting a plurality of first data signals to a plurality of first data lines by a first data driver circuit;
• sequentially outputting a plurality of second data signals to a plurality of second data lines, based on a feedback signal received from the first data driver circuit, by a second data driver circuit, the plurality of second data signals being delayed from the plurality of first data signals;
• supplying each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among a plurality of output channels, wherein each of the first and second data driver circuits comprises a plurality of output channels;
• generating a first internal clock signal, by the first data driver circuit, based on an external clock signal;
• sequentially outputting a plurality of first data signals based on the first internal clock signal and the delay difference;
• and
• supplying, to the second data driver circuit, the feedback signal corresponding to an output timing of a last first data signal from among the plurality of first data signals, the feedback signal being for generating a second internal clock signal used in the second data driver circuit.

A method of driving a display apparatus that comprises a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the method comprising:

• outputting a scan signal to the plurality of scan lines;
• sequentially outputting a plurality of first data signals to a plurality of first data lines by a first data driver circuit;
• sequentially outputting a plurality of second data signals to a plurality of second data lines, based on a feedback signal received from the first data driver circuit, by a second data driver circuit, the plurality of second data signals being delayed from the plurality of first data signals;
• supplying each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among a plurality of output channels, wherein each of the first and second data driver circuits comprises a plurality of output channels;
• generating a first internal clock signal, by the first data driver circuit, based on an external clock signal;
• sequentially outputting a plurality of first data signals based on the first internal clock signal and the delay difference;
• generating a second internal clock signal delayed from the first internal clock signal based on the delay difference;
• and
• outputting the second internal clock signal as the feedback signal to the second data driver circuit.