Methods and apparatus for automated design of semiconductor photonic devices

An apparatus to facilitate design of zero-change CMOS photonic devices, the apparatus comprising:

• at least one user interface including at least one display device;
• at least one processor communicatively coupled to the at least one user interface;
• and
• a memory coupled to the at least one processor, the memory having electronically stored therein processor-executable instructions and:
• a photonics process design library of photonics parameterized cells (pCells);
• a design rule check (DRC) violation removal function;
• and
• a CMOS technology-dependent parameter file including a plurality of design rules for a host CMOS node, wherein a first design rule of the plurality of design rules specifies a minimum dimension requirement,
• wherein upon execution by the at least one processor of the processor-executable instructions, the at least one processor:
• A) controls the at least one user interface and the at least one display device to facilitate electronic access to the library of photonics pCells to create a plurality of physical property layers for a first photonic device, wherein at least one physical property layer of the plurality of physical property layers for the first photonic device includes at least one orthogonal polygon;
• and
• B) processes the plurality of physical property layers, including the at least one physical property layer including the at least one orthogonal polygon, using the DRC violation removal function and at least the first design rule specifying the minimum dimension requirement, to:
• enlarge and diminish dimensions of the at least one orthogonal polygon to thereby generate at least one transformed orthogonal polygon, wherein all opposite edges of the at least one transformed orthogonal polygon are separated by at least the minimum dimension requirement, and
• automatically generate a plurality of mask design layers for a physical layout of the first photonic device in the host CMOS node, based at least in part on the at least one transformed orthogonal polygon, such that the plurality of mask design layers substantially avoid DRC violations in the host CMOS node.

A method for computer-facilitated design of zero-change CMOS photonic devices, the method comprising:

• A) facilitating access to a library of photonics parametrized cells (pCells) to create, via a user interface, a plurality of physical property layers for a first photonic device, wherein at least one physical property layer of the plurality of physical property layers for the first photonic device is created to include at least one curved structure;
• and
• B) electronically processing the plurality of physical property layers using:
• a design rule check (DRC) violation removal function;
• and
• a CMOS technology-dependent parameter file including a plurality of design rules for a host CMOS node to:
• B1) convert the at least one curved structure to at least one orthogonal polygon representing the at least one curved structure in the at least one physical property layer;
• and
• B2) automatically generate a plurality of mask design layers for a physical layout of the first photonic device in the host CMOS node, such that the plurality of mask design layers substantially avoid DRC violations in the host CMOS node.