Using unused wires on very-large-scale integration chips for power supply decoupling

An apparatus for using unused wires on VLSI chips for power supply decoupling, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:

• generating a VLSI chip design by:
• identifying floating wires in a VLSI chip, wherein the floating wires are disconnected from power rails;
• placing a via at each intersection between each floating wire and a power rail;
• determining a number of design rule violations for each via at each intersection;
• resolving the design rule violations for each via not on a major power rail, including keeping each via not on a major power rail with resolvable design rule violations and removing each via not on a major power rail with unresolvable design rule violations;
• resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail, including keeping each via on a major power rail with resolvable design rule violations and removing each via on a major power rail with unresolvable design rule violations;
• after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via;
• and
• for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

A computer program product for using unused wires on VLSI chips for power supply decoupling, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

• generating a VLSI chip design by:
• identifying floating wires in a VLSI chip, wherein the floating wires are disconnected from power rails;
• placing a via at each intersection between each floating wire and a power rail;
• determining a number of design rule violations for each via at each intersection;
• resolving the design rule violations for each via not on a major power rail, including keeping each via not on a major power rail with resolvable design rule violations and removing each via not on a major power rail with unresolvable design rule violations;
• resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail, including keeping each via on a major power rail with resolvable design rule violations and removing each via on a major power rail with unresolvable design rule violations;
• after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via;
• and
• for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.