Integrated circuit and method of manufacturing same

An integrated circuit, comprising:

• a set of gates having a first gate and a second gate separated from each other in a first direction by a first pitch, the set of gates extending in a second direction different from the first direction and being located on a first level;
• a first metal over diffusion region extending in the second direction, and being located on the first level;
• a first conductive structure extending in the first direction and being located on a second level different from the first level;
• a second conductive structure extending in the first direction, being separated from the first conductive structure in the second direction and being located on the second level;
• a first via between the first conductive structure and the first gate of the set of gates, the first via coupling the first conductive structure to the first gate of the set of gates, and the first via being located where the first conductive structure overlaps the first gate of the set of gates;
• a second via between the second conductive structure and the first metal over diffusion region, the second via coupling the second conductive structure to the first metal over diffusion region, and the second via being located where the second conductive structure overlaps the first metal over diffusion region;
• a third conductive structure extending in the first direction, being separated from the first conductive structure and the second conductive structure in the second direction and being located on the second level;
• and
• a third via between the third conductive structure and the second gate of the set of gates, the third via coupling the third conductive structure to the second gate of the set of gates, and the third via being located where the third conductive structure overlaps the second gate of the set of gates.

A method of forming an integrated circuit, the method comprising:

• generating, by a processor, a layout design of the integrated circuit, the layout design having a set of design rules, wherein the generating of the layout design comprises:
• placing a set of gate layout patterns and on a first layout level, the set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, each of the layout patterns of the set of gate layout patterns being separated from an adjacent layout pattern of the set of gate layout patterns in a first direction by a first pitch, the set of gate layout patterns extending in a second direction different from the first direction;
• placing a cut feature layout pattern over the set of gate layout patterns, the cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, the cut feature layout pattern extending in the first direction and overlapping at least a first gate layout pattern of the set of gate layout patterns;
• placing a first metal over diffusion layout pattern on the first layout level, the first metal over diffusion layout pattern corresponding to fabricating a first metal over diffusion region of the integrated circuit, and the first metal over diffusion layout pattern extending in the second direction;
• placing a first conductive feature layout pattern on a second layout level different from the first layout level, the first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and the first conductive feature layout pattern extending in the first direction;
• placing a second conductive feature layout pattern on the second layout level, the second conductive feature layout pattern corresponding to fabricating a second conductive structure of the integrated circuit, the second conductive feature layout pattern extending in the first direction, and being separated from the first conductive feature layout pattern in the second direction;
• placing a first via layout pattern between the first conductive feature layout pattern and the first gate layout pattern of the set of gate layout patterns, the first via layout pattern corresponding to fabricating a first via, the first via coupling the first conductive structure to the first gate of the set of gate structures, and the first via layout pattern being located where the first conductive feature layout pattern overlaps the first gate layout pattern of the set of gate layout patterns;
• and
• placing a second via layout pattern between the second conductive feature layout pattern and the first metal over diffusion layout pattern, the second via layout pattern corresponding to fabricating a second via, the second via coupling the second conductive structure to the first metal over diffusion region, and the second via layout pattern being located where the second conductive feature layout pattern overlaps the first metal over diffusion layout patterns;
• manufacturing the integrated circuit based on the layout design, the integrated circuit having the first gate of the set of gate structures;
• and
• removing a portion of the first gate of the set of gate structures to form a first gate structure and a second gate structure, and the cut feature layout pattern identifying a location of the removed portion of the first gate of the set of gate structures.