Method and system for generating validation tests

A non-transitory computer readable storage medium for amending a validated scenario for generating a validation test, having stored thereon instructions that when executed by a processor will cause the processor to:

• obtain, using a processor, the validated scenario for generating a test for a design under test having a faulty component, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph;
• analyze, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with the faulty component of the design under test;
• and
• upon identifying the identified action, amend, using the processor the validated scenario by removing the identified action from the graph to provide an amended validated scenario.

A system for amending a validated scenario for generating a validation test, the system comprising:

• a memory and
• a processor configured to:
• obtain, using a processor, the validated scenario for generating a test for a design under test having a faulty component, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph;
• analyze, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with the faulty component of the design under test;
• and
• upon identifying the identified action, amend, using the processor the validated scenario by removing the identified action from the graph to provide an amended validated scenario.