Integrated circuit buffering solutions considering sink delays

A system for optimizing timing in a VLSI circuit, the system comprising:

• a memory;
• and
• a processor communicatively coupled to the memory, wherein the processor is configured to perform a method comprising:
• determining a most critical delay and a sum of critical delays for each solution in a set of buffer solutions for the VLSI circuit;
• quantifying, for each solution, a relationship between the most critical delay and the sum of critical delays;
• comparing each solution's relationship to the relationship of each other solution in the set of solutions;
• identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions;
• and
• pruning the at least one solution from the set of solutions.

A computer program product for optimizing timing in a VLSI circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:

• determining a most critical delay and a sum of delays for each solution of a set of buffer solutions for the VLSI circuit;
• quantifying, for each solution, a relationship between the most critical delay and the sum of delays;
• comparing each solution's relationship to the relationship of each other solution in the set of solutions;
• identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution of the set of solutions to have a worse relationship between the most critical delay and the sum of delays than the other solutions in the set of solutions;
• and
• pruning the at least one solution from the set of solutions.